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Abstract— In this research, we focus on analytical reliability assessment. The reliability of particular conditions of voltage, temperature and degradation will be reported to device parameters. Such as the same effect on analogue or digital device performance like SRAM cell and combined circuits. In this research article, we are faced with some research questions to investigate the impact of reliability on comparator circuits. The reliability analysis under the parameters of Positive Bias Temperature Instability (PBTI), Negative Bias Temperature Instability (NBTI) and Hot Carrier Injection (HCI) are performed. In this study, we considered which MOSFET was the most affected and least affected by the comparator circuit. Like all analogue and digital circuits, reliability has caused a circuit that does not work because it increases the trap between the source and the drain of every single MOSFET. Large-scale assessment reliability has shown that the effect of every single MOSFET leads to the misleading conduct of comparator and ultimately causing damages. The precision of the comparator is exposed to this research with varying aspects. The total simulation work is performed using the 45nm technology cadence virtuoso.


Keywords— Reliability, Comparator, CMOS Technology, HCI, NBTI, PBTI and Ageing.

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                                                                                                                                                        I.            Introduction

A serious threat to the expansion of Bias Temperature Instability (BTI) which alters the execution of the VLSI circuit designed by CMOS Technology. NBTI greatly affects the temperature performance parameters such as reliability problems, and the tolerance voltage of a transistor, and the saturation transconductance of PMOS current. Similarly, NMOS transistors are affected by PBTI, but the effect PBTI, VLSI circuit chip is less important compared to the effect of NBTI, in particular in the Si02 layer case. Including NBTI and PBTI have another reason to compromise the reliability of the Hot Carrier Injector (HCI). Reducing the device reduces the duration of PMOS and NMOS transistors and their functionality is significantly degraded.

As technology grows, the performance of the device is increased by decreasing the size of the transistors that affect the life of the design. Reliability means the capability of a method to maintain defined behaves in all conditions. At this nanometre age, most manufacturing faults are contemporaneous and guilty for the destruction of the useful life of the device. The procedure deviation means changes in the properties of the transistor (length, width and thickness of the oxide in the manufacture of the device.) In the variant of the process, there are labour constraints because of nanoscale technology like degradation condition to 250nm,180nm, 90nm, 45nm and 32nm, we have to reduce the mask, but we cannot able to reduce the mask as it is fixed by 136nm masking  scale.

This research paper deals with reliability, many problems to be identified mainly by the variation of PBTI, HCI and NBTI. In HCl, both PMOS and NMOS are concerned, in PBTI only NMOS is distressed and PMOS influences traps only in NBTI. Useful life is greatly reduced by the outflow current generated in the device and maximum of the circuits are based on confidence in the dispersion temperature. HCl affects the reliability of CMOS devices; causing the voltage rise below the threshold and reducing the carrier mobility, which is additional in NMOS transistor. When stratagem design is biased high Vds devices, HCI is a very reliant aspect. At NBTI when the voltage is pragmatic to the port of the PMOS devices, the threshold voltage will increase. It quickens the rise in temperature and rises the dispersion current and the transverse current. PBTI is also a problem of reliability, but is less important in the performance of the design.

In technology, VLSI expands portable design applications such as mobile phones, laptops, PDAs, electronic instruments and systems. The comparator means that it is used to compare two binary words for equality. Parameters, such as response speed and maximum bandwidth usage, are paid by operating amplifier architecture. The use of an op-amp as a comparator principals to an inefficient condition where the current transmission fraction is truncated. The reliability analysis has proven that it does contribute towards increasing the sensitivity of the comparator. Reliability has also proven that it could increase the vulnerability of the least sensitive parts of the comparator as disclosed in Fig.1.Fig. 1. CMOS design of comparator

                                                                                                                                   II.            Impact of PBTI on MOSFET


PBTI mainly occurs in NMOS devices since the operating voltage of the NMOS gate drain is largely positive or we can say that the NMOS device is affected positively (Vgs> 0) and has temperature dependence. PBTI effect is negligible compared to NBTI and HCI. It presents itself as a technology problem and metal gate High-K gate stack

This problem occurs when negative carriers are trapped in the silicon / oxide interface because the oxide or the voltage (Vgs> 0), a temperature dependence. You can see the support of negative movements.

Positive bias temperature instability (PBTI) is similar to the simulated hot-carrier injection (HCI), but there are different sets of model parameters and degradation life. If the parameters defined life PBTI, PBTI then the effects are simulated; On the other hand, they skipped. Both of these effects can be simulated HCl and PBTI together or separately. To stimulate PBTI, the following models are required of the oxide layers.

Fig. 2. Movement of carrier due to PBTI


                                                                                                                                III.            Impact of NBTI on MOSFET

Negative bias temperature instability (NBTI) affects the drain current, Vth, etc., of the PMOS transistors. Due to the variance in uniform band voltage, the NMOS transistor has a insignificant even of holes in the feed and consequently, performs not endure from NBTI degradation.

In a PMOS transistor, here are two phases of NBTI contingent upon the bias ailment of the gate. During the phase 1 when Vg=0 (i.e., Vgs=-Vdd), interface traps are generated diffusing the hydrogen atoms broken from Si-H bonds near to the gate. This phase is stated as “stress” or “static NBTI”. In phase 2, when Vg=Vdd (i.e., Vgs=0), the PMOS device is under pure recovery as hydrogen atoms closer to the interface dispersed in return to the interface and strengthen the wrecked Si-H bonds. This phase is stated as “recovery” and has a momentous effect on the appraisal of NBTI during the forceful interchanging in digital operations. However, in analogue applications recovery is unlikely to happen as the transistors are always undergoing stress when operating.

Fig. 3. Movement carrier due to NBTI


Based on this reaction-diffusion model and considering the simplest case, in which the gate is under a constant stress with a DC voltage, the shift of threshold voltage can be given by

where n is the period interpreter for NBTI which indicates the dilapidation rate. For a H2 based dissemination standard, n=1/6 and for an H centred ideal, n=1/4. Kv has an exponential necessity dependency on temperature (T) and electric field in the dielectric and this is called the static model.

Where q is the electron charge, k is the Boltzmann constant, Cox is the oxide capacitance per unit area, Eox is the vertical electric field across the oxide and tox is the oxide chunkiness.

                                                                                                                                  IV.            Impact of HCI on MOSFET

Hot carrier injection is a further deprivation mechanism perceived in MOSFETs. The main source of heat on MOSFET’s channel during circuit operation, rather than “anode”, as anode-hole injection models. These powerful carriers can penetrate into the oxidation of the surface and the generated electrons or holes inside the channel or heating conductors. In this process, injected carriers generate interface or bulk oxide deficiencies, and as a result, the MOSFET features such as the initial voltage, etc. are reduced over time.


Hot carrier pressure conditions are intrinsic in the CMOS circuit operation. Figure 1(a) shows the CMOS inverter with feedback terminal A and output terminal. When the VA is increased (VDD), the PMOS off experiences NMOS, TDDB pressure. NMOS’s gate terminal, VG = VA, low to high (= 0 V) switches, canal bias, VD = VB, increases. VG ~ VD / 2 (not VDD / 2!), The NMOS goes through the maximum heat carrier pressure situation (given below). Finally, when the VA is low, the NMOS off and the PMOS belongs to NBTI and TDDB. This is a high-to-low low VA (which is not a constant DC component) which can contribute to HCI during inverter operation.


Fig. 4. Flow of carrier due to HCI


The degradation of hot-carrier models in MOS transistors includes:

• A model to calculate the current substrate (NMOSFET, PMOSFET) and gate (PMOSFET)

• A life model that calculates the Hot-carrier circuits that operate under experimental results in accelerated test conditions

• Ageing model that describes the degradation characteristics of transistors in the voltage function: this model type parameters SPICE model for simulation of degraded circuit performance degraded.


                                                                                              V.            SIMULATED RELIABILITY GRAPHS AND RESULTS

Reliability results are simulated for each NMOS & PMOS used in the simulated circuit. In this paper we simulated the parameters like NBTI, HCI and Ageing below the stress circumstances of Voltage, current and temperature. The result of PBTI was negligible so it has been neglected in the paper. Only HCI & NBTI effects are discussed. The circuit of comparator consists of 10 MOSFETS which are of 06 NMOS and 04 PMOS. This designed technology is known as CMOS technology.

Effect in PMOS due to NBTI

Table – 1 presents the Maximum absolute Vgs & Vds values of PMOS used in circuit at 0.7V, 1V & 1.5V supply voltages for transistors under NBTI condition. 

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